[CODE type=vhdl]
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all; entity exadd is
Port ( put1 : in std_logic_vector(3 downto 0);
put2 : in std_logic_vector(3 downto 0);
addsu : out std_logic_vector(3 downto 0));
end exadd;architecture ex of exadd is begin
process (put1, put2)
begin
if put1 > put2 then
addsu <= put1 + put2;
else
addsu <= put2 - put1;
end if;
end process;
end ex;
[/CODE]
입력받는 두 수를 비교해서..
입력 받은 두 수와 덧셈, 뺄셈 하는 것..
시뮬레이터 결과:
※ VHDL 조낸 싫다..
