[CODE type=vhdl]
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity machine is
port (clk,reset: in std_logic;
      inputs : in std_logic;
  counter: out std_logic_vector (0 to 2);
    comb_outputs: out std_logic_vector (0 to 1));
end machine;

architecture behavior of machine is
signal b,c,d,e: std_logic_vector (0 to 2):="000";
signal a: std_logic_vector(0 to 1);
  type states is (st0, st1, st2, st3);
signal present_state, next_state: states;
begin

  registe: process (reset,clk,inputs)
begin          
 if reset = '1' then
  present_state <= st0; -- async reset to st0

 elsif rising_edge(clk) and inputs ='1' then
  present_state <= next_state; -- transition on clock
 
 
   end if;
       
end process;

transitions: process(present_state,inputs)
begin
 case present_state is -- describe transitions
  when st0 => -- and comb. outputs
   comb_outputs <= "00";
    a<="00";
  if inputs = '0' then
    next_state <= st0; -- hold
    else
    next_state <= st1; -- next state
 
   
   
   
   end if;
  when st1 =>
   comb_outputs <= "01";
     a<="01";
     if inputs = '0' then    -- hold
      next_state <= st1;
    else
    next_state <= st2; -- next state
 
 
   
    end if;
  when st2 =>
   comb_outputs <= "10";
     a<="10";
    if inputs = '0' then
    next_state <= st2; -- hold
    else
    next_state <= st3; -- next state
    
    end if;
  when st3 =>
   comb_outputs <= "11";
     a<="11";
    if inputs = '0' then
    next_state <= st3; -- hold
    else
    next_state <= st0; -- next state
   
   
   end if;
 end case;
end process;

count: process(clk,reset)
begin
  if reset = '1' then
  b <= "000";
c <= "000";
d <= "000";
e <= "000";
  elsif clk'event and clk='1' and inputs='1' then
if a="00" then
  b <= b + 1;
end if;
  if a="01" then
  c <= c + 1;
end if;
if a="10" then
  d <= d + 1;
end if;
if a="11" then
  e <= e + 1;
end if;
 
  end if;

end process;
  counter<=e;

end behavior;
[/CODE]