[CODE type=vhdl]
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity machine is
port (clk,reset: in std_logic;
      inputs : in std_logic;
  counter: out std_logic_vector (0 to 2);
    comb_outputs: out std_logic_vector (0 to 1));
end machine;

architecture behavior of machine is
signal b,c,d,e: std_logic_vector (0 to 2):="000";
signal a: std_logic_vector(0 to 1);
  type states is (st0, st1, st2, st3);
signal present_state, next_state: states;
begin

  registe: process (reset,clk,inputs)
begin          
 if reset = '1' then
  present_state <= st0; -- async reset to st0

 elsif rising_edge(clk) and inputs ='1' then
  present_state <= next_state; -- transition on clock
 
 
   end if;
       
end process;

transitions: process(present_state,inputs)
begin
 case present_state is -- describe transitions
  when st0 => -- and comb. outputs
   comb_outputs <= "00";
    a<="00";
  if inputs = '0' then
    next_state <= st0; -- hold
    else
    next_state <= st1; -- next state
 
   
   
   
   end if;
  when st1 =>
   comb_outputs <= "01";
     a<="01";
     if inputs = '0' then    -- hold
      next_state <= st1;
    else
    next_state <= st2; -- next state
 
 
   
    end if;
  when st2 =>
   comb_outputs <= "10";
     a<="10";
    if inputs = '0' then
    next_state <= st2; -- hold
    else
    next_state <= st3; -- next state
    
    end if;
  when st3 =>
   comb_outputs <= "11";
     a<="11";
    if inputs = '0' then
    next_state <= st3; -- hold
    else
    next_state <= st0; -- next state
   
   
   end if;
 end case;
end process;

count: process(clk,reset)
begin
  if reset = '1' then
  b <= "000";
c <= "000";
d <= "000";
e <= "000";
  elsif clk'event and clk='1' and inputs='1' then
if a="00" then
  b <= b + 1;
end if;
  if a="01" then
  c <= c + 1;
end if;
if a="10" then
  d <= d + 1;
end if;
if a="11" then
  e <= e + 1;
end if;
 
  end if;

end process;
  counter<=e;

end behavior;
[/CODE]

[CODE type=vhdl]
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all; entity exadd is
  Port ( put1 : in std_logic_vector(3 downto 0);
          put2 : in std_logic_vector(3 downto 0);
          addsu : out std_logic_vector(3 downto 0));
end exadd;architecture ex of exadd is begin
process (put1, put2)
  begin
 
  if put1 > put2 then
     addsu <= put1 + put2;
      else
     addsu <= put2 - put1;
 
  end if;
  end process;
end ex;
[/CODE]

입력받는 두 수를 비교해서..
입력 받은 두 수와 덧셈, 뺄셈 하는 것..

시뮬레이터 결과:

#include  
#define snum 5 

int tot[snum]={0}, rank[snum]={0}; 

int mrank()
{   
  int i,j;   
  rank[0] = 1;   

  for ( i = 1; i < snum; i++ )    
    rank[i] = 1; 

  for ( i = 1; i < snum; i++ ){ 
   for( j=0; j < i; j++ ){ 
    if ( tot[i] > tot[j] ){
      //rank[i] = rank[j]; 
      rank[j]++; 
    } else { 
      rank[i]++; 
    } 
  } 
} 
  return 0; 
} 

void main( ){ 
  int kuk[snum], eng[snum], mat[snum], k; 
  float ava[snum]={0}; 
  char name[snum][10]; 
  int i=0; 

  for(i=0; i < snum; i++) { 
    printf("성명:"); 
    scanf("%s", name[i]); 
    printf("국어:"); 
    scanf("%d", &kuk[i]); 
    printf("영어:"); 
    scanf("%d", &eng[i]); 
    printf("수학:"); 
    scanf("%d", &mat[i]); 
    tot[i] = kuk[i] + eng[i] + mat[i]; 
    ava[i] = tot[i] / 3.0f; } k = mrank(); 
    printf("----------------------------------------------------------------------");
    printf("성명 국어 영어 수학 총점 평균 순위"); 
    printf("----------------------------------------------------------------------");
    
    for(i=0; i < snum; i++) { 
      printf("%-10s %-3d %-3d %-3d %-3d %-7.2f %d", name[i], kuk[i], eng[i],mat[i],tot[i], ava[i],rank[i]); 
    } 
    printf("----------------------------------------------------------------------"); 
}